ESD & Latch-Up test

  • MIL - JEDEC - ESDA - IEC standards
  • IC level Human Body Model
  • IC level Machine Model
  • IC level Charged Device Model
  • System level IEC 61000 HBM
  • AEC-Q100 Field Induced Gate Leakage test
  • Static Latch-Up test
  • Dynamic Latch-Up test

MASER Engineering has automatic test equipment for the most common ESD test pulse models. ESD protection circuitry properties are depending on the design and process parameters of an individual IC. ESD test are an important item in the qualification procedure of new devices.

Our Thermo Mk.2 systems can automatically test the ESD performance of small and medium pin count devices (<512). The dedicated Thermo RCDM-3 for Charged Device Model testing is not limited for pin count since it is a dead bug test standard. Another functional destructive behavior of an IC is the latch-up state. Parasitic elements switch the device in an uncontrolled mode, in some cases into destructive mode. Latch-up testing can verify if proper design and process measures are effective to avoid the latch-up state. To test the device, it has to be operational and in a stable mode. Our Mk.2 test systems can generate vectors to set the device in that mode. The best latch-up results are optained by working in close cooperation with our customers engineers.

The automotive industry has defined specific test modes. MASER Engineering has built and qualified this specific test setup for all AEC-Q100 device qualification tests. The IEC 61000 ESD test capability is focusing at conductive or field induced ESD pulses on modules and systems. In a dedicated environment the TESEQ NSG-438 system can inject HBM pulses up to 30kV.

Download here the ESD/Latch-Up test leaflet.